The results of the IPCEI ME/CT project, carried out by ELAPHE pogonske tehnologije d.o.o. from 1 January 2023 to 30 June 2026, are available for licensing to interested companies in the European Economic Area at market price, as a commitment under the state aid scheme.
Results Available for Licensing
Microelectronics for Electric Vehicles (MEEV)
Why license Elaphe technology?
Elaphe is a leading company in the field of integrated propulsion systems for electric vehicles. Within the MEEV project (Microelectronics for Electric Vehicles), part of the European IPCEI ME/CT initiative, we developed advanced semiconductor technology: GaN power electronics and a series of GaAs chips that significantly improve the efficiency, compactness and performance of propulsion systems.
The developed technology is protected by intellectual property rights. We offer licenses to all interested companies in the European Economic Area at market price, on a non-exclusive and non-discriminatory basis. Contact us and together we will find a suitable licensing solution for your needs.
Technologies Offered
Subproject 1 · Result 1
Prototype GaN Power Electronics
Power electronics for controlling wheel electric motors, designed using wide-bandgap transistors (GaN). It enables significantly higher switching frequencies (target: 60 kHz, comparison: 16 kHz with conventional Si technology), higher drivetrain efficiency, and reduced system mass and volume.
Maturity level: validated prototype · IP: patent in the field of electronics design/software code
Subproject 2 · Result 2
Prototype Series of GaAs Chips – Geometry No. 1
Extended Gate Electrode
Gallium arsenide semiconductor chip for thermoelectric converters, intended to convert waste heat back into useful electrical energy. Target properties: leakage current through the control electrode < 200 nA, channel modulation > 30%, ohmic contacts with resistance below 50 Ω.
Maturity level: manufactured and characterized series – suitable for further development · IP: registration of semiconductor circuit topography in the register of protected topographies
Subproject 2 · Result 3
Prototype Series of GaAs Chips – Geometry No. 2
Inverted Structure
Second geometric design of the GaAs chip with an inverted layer structure. In experimental series, an alternative layer arrangement was tested to improve channel modulation and reduce leakage currents. Photolithography masks, fabrication and characterization were carried out within the project.
Maturity level: manufactured and characterized series – suitable for further development · IP: registration of semiconductor circuit topography
Subproject 2 · Result 4
Prototype Series of GaAs Chips – Geometry No. 3
Structure with Insulator
Third geometric design of the GaAs chip with an added insulating layer. Objective: long-term stability of the device’s electrical properties (protection against chip aging) and optimized conversion of waste heat into useful energy with higher efficiency than today’s devices based on the Seebeck effect.
Maturity level: manufactured and characterized series – suitable for further development · IP: registration of semiconductor circuit topography
More About the IPCEI ME/CT Project
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Co-financers and stakeholders
